Senior engineer - High-Speed Signal Integrity (Grenoble)

We are expanding our High-Speed High-Frequency team at the Grenoble Research Center and seeking a Senior Engineer – High-Speed Signal Integrity to contribute to cutting-edge high-speed wireline electrical communication (112 Gbit/s and beyond).

This is an opportunity to collaborate with global R&D teams, shape next-generation SerDes systems, and engage in high-impact research & development in a dynamic and innovative environment.

Location: Grenoble, France

Employment Type: Full-time

Industry: High-Speed Telecom | Signal Integrity | Research & Development

Key Responsibilities:

? Develop high-speed interconnects for 112+ Gbps per lane systems

? Design, simulate & analyze high-speed PCBs and interconnects

? Conduct lab verification using oscilloscopes, VNAs & other high-frequency tools

? Collaborate with HQ technical teams in China for project execution and reviews

? Define technology roadmaps & research strategies for high-speed signal integrity

Required Qualifications:

? Master’s degree or PhD in Electrical Engineering, Information Technology, Communication Engineering, or Electromagnetic Science

? Extensive experience in high-speed telecom/communication hardware design

? Proven track record in 56Gbps+ product development & delivery

? Expertise in high-frequency PCB design, impedance control, and crosstalk management

? Hands-on experience with system-level simulations (PCB, connector & cable-level analog signal simulations)

? Deep understanding of PCB/HDI stack-up design & fabrication limitations

? Preferred Skills:

Knowledge of high-speed SerDes architectures (Rx/Tx SerDes PHY, equalization techniques, CDR, DSP challenges)

Experience with lab testing & high-speed measurements (real-time oscilloscopes, VNAs, simulation correlation)

Familiarity with industry standards (IEEE 802.3, OIF-CEI, InfiniBand, CEI-224G)

Proficiency in technical simulation tools:

• 
  High-Speed Design & Simulation: CST, ANSYS HFSS


• 
  SI Analysis: ADS, Sigrity, MATLAB, Python


• 
  SerDes Modeling: Python, MATLAB, Verilog-A, ADS
  
  Passion for R&D & technology innovation
  

What’s on Offer?

Work on cutting-edge high-speed telecom technologies (112 Gbit/s+ SerDes)

Join a world-class R&D center in Grenoble

Collaborate with industry experts & global technical teams

Shape the future of high-speed signal integrity research

If you're passionate about high-speed signal integrity, eager to drive next-gen innovation, and want to make an impact in global R&D, apply today!

#SignalIntegrity #HighSpeedEngineering #GrenobleCareers #HiringNow